System and method for skew compensating a clock signal and for capturing a digital signal using the skew compensated clock signal

ABSTRACT

A synchronized mirror delay circuit is used to generate an internal clock signal from an external clock signal applied to the synchronized mirror delay. The internal clock signal is then coupled through a clock tree, and a feedback signal is generated that is indicative of the propagation delay of the internal clock signal through the clock tree. The feedback signal is applied to the synchronized mirror delay to allow the synchronized mirror delay to delay the internal clock signal by a delay interval that compensates for the propagation delay in the clock tree. A lock detector may be used to initially generate the internal clock signal directly from the external clock signal. A fine delay circuit that delays the internal clock signal in relatively fine increments may be used to couple the internal clock signal to the clock tree.

TECHNICAL FIELD

[0001] This invention relates to electronic devices that are operated insynchronism with a clock signal, and more particularly to a system andmethod for compensating for variations in the propagation delay of clocksignals in comparison to the propagation delay of other signals.

BACKGROUND OF THE INVENTION

[0002] The operating speed of electronic devices, such as memorydevices, can often be increased by synchronizing the operation of thedevice to a clock signal. By operating the device synchronously, thetiming at which various function occur in the device can be preciselycontrolled thereby allowing the speed at which these functions areperformed to be increased by simply increasing the frequency or speed ofthe clock signal. However, as the speeds of clock signals has continuedto increase with advances in semiconductor fabrication techniques, thepropagation delays of clock signals within integrated circuit deviceshave become a problem. More specifically, internal clock signals areoften generated from an external clock signal applied to the integratedcircuit device. These internal clock signals are coupled throughout theintegrated circuit device to control the timing of a variety ofcircuits. The times required for the internal clock signals to propagateto these circuits is difficult to either control or predict. As clockspeeds continue to increase, the unpredictable and/or uncontrolledvariations in internal clock signal propagation times can cause internalclock signals to be applied to circuits either too early or too late toallow the circuits to properly perform their intended functions. Thisproblem, known as “clock skew,” threatens to limit the speed at whichintegrated circuit devices can function.

[0003] Various solutions have been proposed to address this clock skewproblems. Some of these solutions are described in Takanori Saeki etal., “A Direct-Skew-Detect Synchronous Mirror Delay forApplication-Specific Integrated Circuits,” IEEE Journal of Solid-StateCircuits, Vol. 34, No. 3, March 1999. The article by Takanori Saeki etal. describes both open-loop and closed-loop clock skew compensationapproaches. Closed-loop approaches include the use of phase-locked loops(“PLL”) and delay-locked loops (“DLL”) to synchronize the phase ortiming of an internal clock signal to the phase or timing of an externalclock signal used to generate the internal clock signal. Theseclosed-loop approaches use a feedback signal to indicate the timingvariations within the device. A phase comparator, such as a phasedetector, is required to compare the phase or timing of the feedbacksignal to the phase or timing of a reference signal. Unfortunately, asignificant amount of time may be required to achieve lock of the PLL orDLL.

[0004] Open-loop designs described in the Takanori Saeki et al. articleinclude synchronized mirror delay (“SMD”) circuits and clocksynchronized delay (“CSD”) circuits. CSD circuits generally include avariable delay line, usually a series of inverters, and latch circuitsfor selecting the output of one of these inverters as the delay lineoutput. An internal clock signal is applied to the CSD circuit, and themagnitude of the delay provided by the CSD circuit is controlled in anattempt to set the phase or timing at which the internal clock signal isapplied to an internal circuit. SMD circuits are basically the same asCSD circuits except that CSD circuits require the use of latches tostore information. On the other hand, SMD circuits require speciallyshaped input clock signals. In order to generate internal clock signalson both the rising and falling edges of a clock signal (i.e., doubledata rate operation), SMD circuits, but not CSD circuits, require twovariable delay lines, one for the clock signal and one for itscompliment. In view of the similarity of CSD circuits and SMD circuits,they will be generically referred to herein as CSD/SMD circuits.

[0005] A conventional CSD/SMD circuit 10 described in the Takanori Saekiet al. article is shown in FIG. 1. An external clock signal XCLK isapplied to an input buffer 12, and the output of the buffer 12 isapplied to a delay model circuit 14. The output of the delay modelcircuit 14 is coupled through a measurement delay line to set a delay ofa variable delay line 20. The delay of both the measurement delay line16 and the variable delay line 20 is set to integer multiples of a clockperiod of the external clock signal less the delay of the delay modelcircuit 14, i.e., n*tCLK−d_(mdl), where n is an integer, tCLK is theperiod of the XCLK signal, and d_(mdl) is the delay of the delay modelcircuit 14. The variable delay line 20 outputs a clock signal to a clockdriver 24. The clock driver 24 then outputs an internal clock signalICLK to an internal clock line 28. The internal clock line 28 is coupledto a number of internal circuits 32 through respective circuit paths,which are collectively known as a “clock tree” 36.

[0006] The external clock signal XCLK is coupled through the inputbuffer 12 with a delay of d₁, through the measurement delay line 16 witha delay of d₂, through the variable delay line 20 with a delay of d₃,and through the clock driver 24 with a delay of d₄. For the phase of theinternal clock signal ICLK to be synchronized to the phase of theexternal clock signal XCLK before the CSD/SMD circuit 10 has beenlocked, the sum of these delays, i.e., d₁+d_(mdl)+d₂+d₃+d₄, should beequal to integer multiples of one period tCLK of the external clocksignal XCLK.

[0007] In operation, the delay d₃ of the variable delay line 20 is setin a conventional manner so that it is equal to the delay of themeasurement delay line 16. The delay d₂ of the measurement delay line 16is set by conventional means to the difference between integer multiplesof the period tCLK of the external clock signal XCLK and the delayd_(mdl) of the delay model circuit 14, i.e., d₂=n*tCLK−d_(mdl). Thus,after one clock period tCLK, the delay d₃ of the variable delay line 20has been determined. The total delay from the input of the input buffer12 to the internal clock line 28 is given by the equation: d₁+d₃+d₄. Thedelay d_(mdl) of the delay model circuit 14 is set to the sum of thedelay d₁ of the input buffer 14 and the delay d₄ of the clock driver 24.This can be accomplished by implementing the delay model circuit 14 witha “dummy” input buffer 42 and a “dummy” clock driver 44. The dummy inputbuffer 42 is preferably identical to the input buffer 12 and thus alsoprovides a delay of d₁. Similarly, the dummy clock driver 44 ispreferably identical to the clock driver 24 and thus also produces adelay of d₄. Using the equation d₃=d₂=n*tCLK−d_(mdl), the above equationd₁+d₃+d₄ for the total delay can be rewritten as: d₁+n*tCLK−d_(mdl)+d₄.Combining this last equation and the equation d_(mdl)=d₁+d₄ allows theequation for the total delay from the input of the input buffer 12 tothe ICKL line 28 to be rewritten as: d₁+n*tCLK−d₁−d₄+d₄. This lastequation can be reduced to simply n*tCLK, or 1 clock period of theexternal clock signal XCLK, assuming the delay of the delay modelcircuit 14 is less than a period of the external clock signal, i.e.,d_(mdl)<tCLK. Thus, by using the delay model circuit 14 to model thedelay d₁ of the input buffer 12 and the delay d₄ of the clock driver 24,the phase of the internal clock signal ICLK can be synchronized to thephase of the external clock signal XCLK. Moreover, the total lock time,including the delay through the delay model circuit 14 and themeasurement delay line 16, is equal to d₁+d_(mdl)+d₂+d₃+d₄, which can bereduced to 2n*tCLK. Therefore, this phase matching of the ICLK signalcan be accomplished after only two periods of the external clock XCLKsignal so that the integer “n” may be set equal to one.

[0008] Although the SMD/CSD circuit 10 shown in FIG. 1 can properlysynchronize the phase of the internal clock signal ICLK to the phase ofthe external clock signal XCLK, it does so only at the internal clockline 28. The SMD/CSD circuit 10 does not compensate for propagationdelays in the clock tree 36 used to couple the internal clock signalICLK from the internal clock line 28 to the internal circuits 32.

[0009] An SMD/CSD circuit 48 somewhat similar to the SMD/CSD circuit 10can be used in a clock skew compensation circuit 50 as shown in FIG. 2to compensate for propagation delays in a clock tree. The SMD/CSDcircuit 48 is shown as being used to generate an internal clock signalfrom an external clock signal XCLK that is used to latch an externaldata signal DATA in a latch 52. The external data signal is coupled tothe latch through a data input buffer 56 having a delay of d₁. Theexternal clock signal XCLK is applied to an input buffer 60 having adelay of d₂, and the output of the input buffer 60 is applied through adelay model circuit 62 to a measurement delay line 64. The delay modelcircuit 62 has a delay of d_(mdl), and the measurement delay line 64 hasa delay of d₃. The output of the input buffer 60 is also applied to avariable delay line 70 that is controlled so that it has the same delayd₃ as the measurement delay line 64, as previously explained. The outputof the variable delay line 70 is applied to a clock driver 74 having adelay of d₄. Finally, the internal clock signal has a propagation delayof d₅ as it is coupled through a clock tree 78 from the clock driver 74to the clock input of the latch 52.

[0010] The total delay from the input of the input buffer 60 to theclock input of the latch 52 is thus given by the equation: d₂+d₃+d₄+d₅after the delay of the variable variable delay line 70 is determined.For the internal clock signal to enable the latch 52 to capture the datasignal, the total delay should be reduced by the delay d₁ of the DATAsignal propagating through the data input buffer 56. The timingrelationship between the XCLK signal and the DATA signal as they areapplied to the latch 52 will then be the same as the timing relationshipbetween the XCLK signal and the DATA signal as they are externallyreceived. The XCLK signal is coupled to the latch with a total delay of:d₂+d₃+d₄+d₅. Substituting d₃=[n*tCLK−d_(mdl)] in the above equationyields for the total delay: d₂+[n*tCLK−d_(mdl)]+d₄+d₅. If the delaymodel circuit 62 models not only the delays of the input buffers 56, 60and the clock driver 74, but also the delay d₅ of the clock tree 78, thedelay of the delay model circuit 62 is given by the formula:d_(mdl)=d₂−d₁+₄+d₅. The above equation for the total delay can then beexpressed as: d₂+[n*tCLK−d₂+d₁−d₄−d₅]+d₄+d₅. This equation can bereduced to simply n*tCLK+d₁, or n periods of the XCLK signal plus thedelay of the DATA signal through the input buffer 56. Letting n=1, theXCLK signal will thus be applied to the latch 52 one clock periods afterthe DATA signal is applied to the latch 52 so that the XCLK and DATAsignals will have the same timing relationship at the latch 52 as theXCLK and DATA signals have at the external input terminals. To calculatethe time for the SMD/CSD circuit 48 to achieve lock, the total delaytime should be increased by the delay d_(mdl) of the delay model circuit62 and the delay d₃ of the measurement delay line 64. Thus, the totaltime to achieve lock isd₂+d_(mdl)+(n*tCLK−d_(mdl))+(n*tCLK−d_(mdl))+d₄+d₅, which, for n=1 andd_(mdl)<tCLK, can be reduced using the formula d_(mdl)=d₂−d₁+d₄+d₅ to2*tCLK+d₁.

[0011] The clock skew compensation circuits 50 improves the operation ofsynchronous digital circuits by attempting to compensate for propagationdelays in a clock tree 78 coupled to a latch 52. As explained above, thecircuit 50 attempts to compensate for clock tree propagation delays byattempting to model the propagation delay of the clock tree 78. However,it is significantly more difficult to model the propagation delay of theclock tree 78 compared to modeling the propagation delay of othercircuits, such as the input buffers 56, 60 and the clock driver 74. Theinput buffers 56, 60 and clock driver 74, for example, can be modeled bysimply including “dummy” buffers and drivers in the delay model circuit62. But it is generally not practical to include an entire clock tree inthe delay model circuit 62. Moreover, propagation delays can bedifferent in different branches of the clock tree 78, and thepropagation delay in even a single branch of the clock tree 78 can varyas a function of time and temperature, for example. With the continuedincreases in clock speed needed to increase the operating speed ofintegrated circuit devices, these variations in the propagation delaysin the clock tree 78 can prevent the proper operation of integratedcircuit devices.

[0012] There is therefore a need for a suitable system and method forcompensating for clock signal skew as internal clock signals are coupledto various circuits through a clock tree.

SUMMARY OF THE INVENTION

[0013] A clock skew compensation circuit according to the presentinvention includes a synchronized mirror delay or clock synchronizeddelay having a measurement delay line and a variable delay line. A clocksignal is coupled to the variable delay line of the synchronized mirrordelay, optionally through a buffer that may delay the clock signal by afirst delay value. A clock tree is coupled to an output terminal of thesynchronized mirror delay. The clock tree generates a feedback signalthat is coupled to an input terminal of the measurement delay line inputterminal. The feedback signal corresponds to the propagation delay ofthe clock signal being coupled through the clock tree. The clock signalcoupled through the clock tree may be used to capture a digital signalin a suitable circuit, such as a latch.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014]FIG. 1 is a block diagram of a conventional synchronized mirrordelay circuit that can be used to compensation for some clock signalskew in integrated circuit devices.

[0015]FIG. 2 is a block diagram of a conventional clock skewcompensation circuit using a synchronized mirror delay circuit.

[0016]FIG. 3 is a block diagram of a clock skew compensation circuitaccording to one embodiment of the invention.

[0017]FIG. 4 is a block diagram of a clock skew compensation circuitaccording to another embodiment of the invention.

[0018]FIG. 5 is a block diagram of a memory device using a clock skewcompensation circuit in accordance with an embodiment of the invention.

[0019]FIG. 6 is a block diagram of a computer system using the memorydevice of FIG. 5.

DETAILED DESCRIPTION OF THE INVENTION

[0020] A clock skew compensation circuit 110 according to one embodimentof the invention is shown in FIG. 3. The compensation circuit 110includes an SMD/CSD circuit 114 having a measurement delay line 116 anda variable delay line 118 that operate in the same manner as the SMD/CSDcircuits described with reference to FIGS. 1 and 2. An external clocksignal XCLK is applied to the SMD/CSD circuit 114 through an inputbuffer 120 that introduces a delay of d₁. Each of the delay lines 116,118 in the SMD/CSD circuit 114 introduces a delay of d₂. The output ofthe SMD/CSD circuit 114 is applied to one input of a multiplexer 124that is controlled by a lock detector 130. The lock detector 130 causesthe multiplexer 124 to initially couple the output of the input buffer120 to a clock tree 140, which, in turn, is coupled to an internal dataor “DQ” path 144. Once the measurement delay line 116 has set the properdelay of the variable delay line 118, the lock detector 130 causes themultiplexer 124 to couple the output of the SMD/CSD circuit 114 to alatch (not shown) in the tree 140, which, in turn, strobes data througha signal line 142 and through the DQ path 144. As previously mentioned,it requires only two periods of the external clock XCLK signal for theproper delay of the variable delay line 118 to be set. Thus, the lockdetector 130 can be implemented by a conventional circuit that simplycounts two clock pulses and then generates a signal to switch themultiplexer 124.

[0021] Unlike the clock skew compensation circuits 50 shown in FIG. 2,the clock skew compensation circuit 110 does not use any circuit tomodel the delay of the clock tree 140. Instead, the delay of the clocktree is determined from the clock tree 140 itself. More specifically, afeedback signal from a chosen node of the clock tree 140 is coupledthrough a line 148 to the input of the measurement delay line 116through a delay model circuit 150. However, the delay model circuit 150does not model the delay of the clock tree 140. Instead, the delay modelcircuit 150 models only the delay d₁ of the input buffer 120 and the DQpath 144. As previously explained, it is substantially easier to model aclock driver or a single data path than it is to model a clock tree. Inthe clock skew compensation circuit 110, the delay model circuit 150 isimplemented by a “dummy” input buffer 154, which is identical to theinput buffer 120, and an additional delay circuit 155, which provides adelay corresponding to the delay of the DQ path.

[0022] The delay of the clock tree 140 from the output of the SMD/CSDcircuit 114 to the chosen node can be designated as d₃. Since thefeedback signal coupled to the input of the delay model circuit 150corresponds to the delay of the clock tree 140, the signal applied tothe input of the measurement delay line 116 corresponds to the delay ofthe input buffer 120 plus the delay of the clock tree 140. The signalapplied to the measurement delay line 116 thus replicates the signalsthat the delay model circuits provide to the measurement delay lines inthe clock skew compensation circuits 50 shown in FIG. 2.

[0023] The equations explaining the operation of the clock skewcompensation circuit 110 are as explained below with the assumption thatn=1 and d_(mdl)<tCLK. As previously mentioned, d₁ is the delay of theinput buffer 120, d₂ is the delay of the delay of the SMD/CSD circuit114, d₃ is the delay of the clock tree 140 to the node where thefeedback signal is taken, and d₄ is the delay of the DQ path 144: Thedelay d₂ of the SMD/CSD circuit 114 is given by the equationd₂=tCLK−d₁−d₃−d₄. Substituting this equation in the earlier equationprovides: d₁+[tCLK−d₁−d₃−d₄]+d₃+d₃, which may be expanded tod₁+tCLK−d₁−d₃−d₄+d₃+d₄, which can be simplified to tCLK, or one periodof the external clock signal XCLK. The total time to achieve lock isgiven by the formulad₁+d₃+d_(mdl)+(tCLK−d₃−d_(mdl))+(tCLK−d₃−d_(mdl))+d₃+d₄, which can bereduced to d₁+2tCLK−d_(mdl)+d₄. Using the formula d_(mdl)=d₁+d₄, theformula for calculating the total time to achieve lock can be reduced tosimply 2tCLK.

[0024] The delay lines 116, 118 used in the clock skew compensationcircuit 110 of FIG. 3 may be implemented with series coupled logiccircuits, such as inverters (not shown). In such case, the resolution ofthe delay lines 116, 118, i.e., the minimum delay increments, will belimited to the approximately 200 ps delay time of two logic gates. Withtime interpolation, the resolution chould be improved to a fraction ofthe two logic gate delay, such as about 50 ps. To allow the delay lines116, 118 to interpolate the delay time of each logic circuit, a clockskew compensation circuit 160 as shown in FIG. 4 may be used. Thecircuit 160 uses many of the same components used in the clock skewcompensation circuit 110 of FIG. 3. In the interest of brevity, thesecomponents have been provided with the same reference numerals, and anexplanation of their structure and operation will not be repeated. Theclock skew compensation circuit 160 includes a DLL used to interpolatein fine increments within the minimum resolution of the delay lines 116,118. The DLL includes a fine delay line 92 that can alter the delay ofthe clock signal applied to the clock tree in fine increments. The finedelay is incremented or decremented under control of an UP/DOWN signalgenerated by a phase detector 94. The phase detector 94 compares thephase of the clock signal at the output of the input buffer 120 with thephase of the feedback clock signal from a predetermined node of theclock tree 140. The compensation circuit 160 also differs from thecompensation circuit 110 of FIG. 3 by the inclusion of a clock driver170 for applying the internal clock ICLK signal to the clock tree 140.Also, the compensation circuit 160 includes a latch 52 that uses theICLK signal to capture an external DATA signal.

[0025] The following equation explain the operation of the clock skewcompensation circuit 160, in which d₁ is the delay of the input buffer120, d₂ is the delay of the SMD/CSD circuit 114, d₃ is the delay of thefine delay circuit 92, d₄ is the delay of the clock driver 170, d₅ isthe delay of the clock tree 140 to the node where the feedback signal istaken, and d₆ is the delay of the data driver circuit 56. In order tobalance the load of each output of the clock tree 140, the feedbacksignal is coupled from the tree 140 through a signal line that isindependent from, but has the same electrical length as, the signallines used to couple the clock signal to other circuits, such as to theclock input of the latch 52. The total delay from the external clockterminal where the external clock signal XCLK is applied to the clockinput of the latch 52 is given by the formula: d₁+d₂+d₃+d₄+d₅, whered_(mdl)=d₁−d₆. The delay d₂ of each delay line 116, 118 in the SMD/CSDcircuit 114 is given by the equation d₂=tCLK−d_(mdl)−d₃−d₄−d₅.Substituting the equations for d_(mdl) and for d₂ in the total delayequation yields: d₁+[tCLK−d₁+d₆−d₃−d₄−d₅]+d₃+d₄+d₅, which can besimplified to tCLK+d₆. The ICLK signal will thus be applied to the latch52 one clock period after the DATA signal is applied to the latch 52.The time to achieve lock can be calculated using the procedure describeabove as: d₁+d₆+2[tCLK−d_(mdl)−d₃−d₄−d₅]+[d_(mdl)+d₃+d₄+d₅]+d₃+d₄+d₅,which can be reduced to 2tCLK+d₆.

[0026] Alternatively, rather than include the negative delay d₆ of thedata input buffer 56 in the delay model circuit 150, an additional inputbuffer (not shown) like the buffer 56 can be added between the inputbuffer 120 and the variable delay line 118.

[0027] The clock skew compensation circuits 110, 160 can be used tolatch commands or addresses into and data into and out of a variety ofmemory devices, including the memory device shown in FIG. 5. The memorydevice illustrated therein is a synchronous dynamic random access memory(“SDRAM”) 200, although the invention can be embodied in other types ofsynchronous DRAMs, such as packetized DRAMs and RAMBUS DRAMs (RDRAMS”),as well as other types of synchronous devices. The SDRAM 200 includes anaddress register 212 that receives either a row address or a columnaddress on an address bus 214. The address bus 214 is generally coupledto a memory controller (not shown in FIG. 5). Typically, a row addressis initially received by the address register 212 and applied to a rowaddress multiplexer 218. The row address multiplexer 218 couples the rowaddress to a number of components associated with either of two memorybanks 220, 222 depending upon the state of a bank address bit formingpart of the row address. Associated with each of the memory banks 220,222 is a respective row address latch 226, which stores the row address,and a row decoder 228, which applies various signals to its respectivearray 220 or 222 as a function of the stored row address. The rowaddress multiplexer 218 also couples row addresses to the row addresslatches 226 for the purpose of refreshing the memory cells in the arrays220, 222. The row addresses are generated for refresh purposes by arefresh counter 230, which is controlled by a refresh controller 232.

[0028] After the row address has been applied to the address register212 and stored in one of the row address latches 226, a column addressis applied to the address register 212. The address register 212 couplesthe column address to a column address latch 240. Depending on theoperating mode of the SDRAM 200, the column address is either coupledthrough a burst counter 242 to a column address buffer 244, or to theburst counter 242 which applies a sequence of column addresses to thecolumn address buffer 244 starting at the column address output by theaddress register 212. In either case, the column address buffer 244applies a column address to a column decoder 248 which applies varioussignals to respective sense amplifiers and associated column circuitry250, 252 for the respective arrays 220, 222.

[0029] Data to be read from one of the arrays 220, 222 is coupled to thecolumn circuitry 250, 252 for one of the arrays 220, 222, respectively.The data is then coupled through a read data path to a data outputregister 256, which applies the data to a data bus 258. Data to bewritten to one of the arrays 220, 222 is coupled from the data bus 258through a data input register 260 and a write data path to the columncircuitry 250, 252 where it is transferred to one of the arrays 220,222, respectively. A mask register 264 may be used to selectively alterthe flow of data into and out of the column circuitry 250, 252, such asby selectively masking data to be read from the arrays 220, 222.

[0030] The above-described operation of the SDRAM 200 is controlled by acommand decoder 268 responsive to command signals received on a controlbus 270. These high level command signals, which are typically generatedby a memory controller (not shown in FIG. 5), are a clock enable signalCKE*, a clock signal CLK, a chip select signal CS*, a write enablesignal WE*, a row address strobe signal RAS*, and a column addressstrobe signal CAS*, which the “*” designating the signal as active low.Various combinations of these signals are registered as respectivecommands, such as a read command or a write command. The command decoder268 generates a sequence of control signals responsive to the commandsignals to carry out the function (e.g., a read or a write) designatedby each of the command signals. These command signals, and the manner inwhich they accomplish their respective functions, are conventional.Therefore, in the interest of brevity, a further explanation of thesecontrol signals will be omitted. The CLK signal, shown in FIGS. 3 and 4as the external clock signal XCLK, is preferably coupled through a clockskew compensation circuit in accordance with the invention, such as theclock skew compensation circuits 110, 160 shown in FIGS. 3 and 4,respectively. The compensation circuits 110, 160 can then be used togenerate an internal clock signal ICLK that latches addresses from theaddress bus 214, latches data from the data bus 258, or latched dataonto the data bus 258, as previously explained.

[0031]FIG. 6 shows a computer system 300 containing the SDRAM 200 ofFIG. 5. The computer system 300 includes a processor 302 for performingvarious computing functions, such as executing specific software toperform specific calculations or tasks. The processor 302 includes aprocessor bus 304 that normally includes an address bus, a control bus,and a data bus. In addition, the computer system 300 includes one ormore input devices 314, such as a keyboard or a mouse, coupled to theprocessor 302 to allow an operator to interface with the computer system300. Typically, the computer system 300 also includes one or more outputdevices 316 coupled to the processor 302, such output devices typicallybeing a printer or a video terminal. One or more data storage devices318 are also typically coupled to the processor 302 to allow theprocessor 302 to store data in or retrieve data from internal orexternal storage media (not shown). Examples of typical storage devices318 include hard and floppy disks, tape cassettes, and compact diskread-only memories (CD-ROMS). The processor 302 is also typicallycoupled to cache memory 326, which is usually static random accessmemory (“SRAM”), and to the SDRAM 200 through a memory controller 330.The memory controller 330 normally includes a control bus 336 and anaddress bus 338 that are coupled to the SDRAM 200. A data bus 340 iscoupled from the SDRAM 200 to the processor bus 304 either directly (asshown), through the memory controller 330, or by some other means.

[0032] From the foregoing it will be appreciated that, although specificembodiments of the invention have been described herein for purposes ofillustration, various modifications may be made without deviating fromthe spirit and scope of the invention. Accordingly, the invention is notlimited except as by the appended claims.

1. A clock skew compensation circuit, comprising: a synchronized mirrordelay having an output terminal, a measurement delay line inputterminal, and a variable delay line input terminal; an input bufferhaving an input terminal coupled to receive an external clock signal andan output terminal coupled to the variable delay line input terminal ofthe synchronized mirror delay; and a clock tree coupled to the outputterminal of the synchronized mirror delay, the clock tree having afeedback node, the feedback node being coupled to the measurement delayline input terminal to provide a delayed feedback signal correspondingto a signal coupled from the feedback node of the clock tree.
 2. Theclock skew compensation circuit of claim 1 wherein the input bufferdelays the external clock signal by a first delay value; and wherein theclock skew compensation circuit further comprises a model delay circuitcoupled between the feedback node of the clock tree and the measurementdelay line input terminal, the model delay circuit providing a delaysubstantially equal to the first delay value so that the delayedfeedback signal applied to the measurement delay line input terminalcorresponds to the signal from the feedback node of the clock treedelayed by substantially the first delay value.
 3. The clock skewcompensation circuit of claim 2 further comprising: a clock drivercoupling the output of the synchronized mirror delay to the clock tree,the clock driver providing a delay of a second delay value, and whereinthe model delay circuit further provides a delay substantially equal tothe second delay value so that the delayed feedback signal applied tothe measurement delay line input terminal corresponds to the signal fromthe feedback node of the clock tree delayed by substantially the sum ofthe first delay value and the second delay value.
 4. The clock skewcompensation circuit of claim 1 further comprising: a switch having afirst input terminal coupled to receive the external clock signal, asecond input terminal coupled to the output terminal of the synchronizedmirror delay, an output terminal coupled to the clock tree and a controlterminal for coupling the output terminal to the first input terminalresponsive to a control signal applied to the control terminal having afirst state and coupling the output terminal to the second inputterminal responsive to the control signal having a second state; and adetector coupled to the control input of the switch and being operableto determine when the synchronized mirror delay has stabilized, thedetector being operable to generate the control signal having the firststate prior to determining the synchronized mirror delay has stabilizedand to generate the control signal having the second state responsive todetermining the synchronized mirror delay has stabilized.
 5. The clockskew compensation circuit of claim 4 wherein the detector comprises alogic circuit that is operable to generate the control signal having thefirst state prior to the lapse of a predetermined number of periods ofthe external clock signal, and is operable to generate the controlsignal having the second state responsive to the lapse of thepredetermined number of periods of the external clock signal.
 6. Theclock skew compensation circuit of claim 5 wherein the predeterminednumber of periods of the external clock signal is two periods of theexternal clock signal.
 7. The clock skew compensation circuit of claim 1further comprising: a fine delay line coupled between the output of thesynchronized mirror delay and the clock tree, the fine delay linevarying the delay of the fine delay line responsive to a delay controlsignal applied to a control terminal of the fine delay line; a phasedetector having a first input terminal to an output terminal of the finedelay line, a second input terminal, and an output terminal coupled tothe control terminal of the fine delay line, the phase detectorgenerating the delay control signal as a function of the phasedifference between signal applied to its first and second inputterminals; and a delay model circuit operable to provide a predetermineddelay, the delay model circuit coupling the delayed feedback signal fromthe clock tree to the second input terminal of the phase detector. 8.The clock skew compensation circuit of claim 7 wherein the delay modelcircuit comprises a delay circuit having a delay with a delay magnitudethat is substantially less than the delay of the synchronized mirrordelay.
 9. A clock skew compensation circuit, comprising: an input bufferhaving an output terminal and an input terminal coupled to receive anexternal clock signal; a delay circuit having an output terminal, afirst input terminal coupled to the output terminal of the input buffer,and a second input terminal, the delay circuit being operable togenerate a delay corresponding to the difference between a clock periodof the external clock and a lapse in time between a signal applied tothe first input terminal and a signal applied to the second inputterminal; and a clock tree coupled to the output terminal of the delaycircuit, the clock tree having a feedback node coupled to the secondinput terminal of the delay circuit.
 10. The clock skew compensationcircuit of claim 9 wherein the input buffer delays the external clocksignal by a first delay value; and wherein the clock skew compensationcircuit further comprises a model delay circuit coupled between thefeedback node of the clock tree and the second input terminal of thedelay circuit, the model delay circuit providing a delay substantiallyequal to the first delay value so that the delayed feedback signalapplied to the second input terminal of the delay circuit corresponds tothe signal from the feedback node of the clock tree delayed bysubstantially the first delay value.
 11. The clock skew compensationcircuit of claim 10 further comprising: a clock driver coupling theoutput of the delay circuit to the clock tree, the clock driverproviding a delay of a second delay value, and wherein the model delaycircuit further provides a delay substantially equal to the second delayvalue so that the delayed feedback signal applied to the second inputterminal corresponds to the signal from the feedback node of the clocktree delayed by substantially the sum of the first delay value and thesecond delay value.
 12. The clock skew compensation circuit of claim 9further comprising: a switch having a first input terminal coupled toreceive the external clock signal, a second input terminal coupled tothe output terminal of the delay circuit, an output terminal coupled tothe clock tree and a control terminal for coupling the output terminalto the first input terminal responsive to a control signal applied tothe control terminal having a first state and coupling the outputterminal to the second input terminal responsive to the control signalhaving a second state; and a detector coupled to the control input ofthe switch and being operable to determine when the delay circuit hasstabilized, the detector being operable to generate the control signalhaving the first state prior to determining the delay circuit hasstabilized and to generate the control signal having the second stateresponsive to determining the delay circuit has stabilized.
 13. Theclock skew compensation circuit of claim 12 wherein the detectorcomprises a logic circuit that is operable to generate the controlsignal having the first state prior to the lapse of a predeterminednumber of periods of the external clock signal, and is operable togenerate the control signal having the second state responsive to thelapse of the predetermined number of periods of the external clocksignal.
 14. The clock skew compensation circuit of claim 13 wherein thepredetermined number of periods of the external clock signal is twoperiods of the external clock signal.
 15. The clock skew compensationcircuit of claim 9 further comprising: a fine delay line coupled betweenthe output of the delay circuit and the clock tree, the fine delay linevarying the delay of the fine delay line responsive to a delay controlsignal applied to a control terminal of the fine delay line; a phasedetector having a first input terminal to an output terminal of the finedelay line, a second input terminal, and an output terminal coupled tothe control terminal of the fine delay line, the phase detectorgenerating the delay control signal as a function of the phasedifference between signal applied to its first and second inputterminals; and a delay model circuit operable to provide a predetermineddelay, the delay model circuit coupling the delayed feedback signal fromthe clock tree to the second input terminal of the phase detector. 16.The clock skew compensation circuit of claim 15 wherein the delay modelcircuit comprises a delay circuit having a delay with a delay magnitudethat is substantially less than the delay of the synchronized mirrordelay.
 17. A digital signal capture circuit, comprising: a synchronizedmirror delay having an output terminal, a measurement delay line inputterminal, and a variable delay line input terminal; an input bufferhaving an input terminal coupled to receive an external clock signal andan output terminal coupled to the variable delay line input terminal ofthe synchronized mirror delay; a latch having a clock terminal and aninput signal terminal coupled to receive the digital signal; and a clocktree coupling the output terminal of the synchronized mirror delay tothe clock terminal of the latch, the clock tree having a feedback nodecoupled to the measurement delay line input terminal to provide adelayed feedback signal corresponding to a signal coupled from thefeedback node of the clock tree.
 18. The digital signal capture circuitof claim 17 wherein the input buffer delays the external clock signal bya first delay value; and wherein the clock skew compensation circuitfurther comprises a model delay circuit coupled between the feedbacknode of the clock tree and the measurement delay line input terminal,the model delay circuit providing a delay substantially equal to thefirst delay value so that the delayed feedback signal applied to themeasurement delay line input terminal corresponds to the signal from thefeedback node of the clock tree delayed by substantially the first delayvalue.
 19. The digital signal capture circuit of claim 18 furthercomprising a clock driver coupling the output of the synchronized mirrordelay to the clock tree, the clock driver providing a delay of a seconddelay value, and wherein the model delay circuit further provides adelay substantially equal to the second delay value so that the delayedfeedback signal applied to the measurement delay line input terminalcorresponds to the signal from the feedback node of the clock treedelayed by substantially the sum of the first delay value and the seconddelay value.
 20. The digital signal capture circuit of claim 17 whereinthe input buffer delays the external clock signal by a first delayvalue, and wherein the digital signal is coupled to the latch through adriver circuit that delays the digital signal by a second delay value,and wherein the clock skew compensation circuit further comprises amodel delay circuit coupled between the feedback node of the clock treeand the measurement delay line input terminal, the model delay circuitproviding a delay substantially equal to the first delay value less thesecond delay value.
 21. The digital signal capture circuit of claim 17further comprising: a switch having a first input terminal coupled toreceive the external clock signal, a second input terminal coupled tothe output terminal of the synchronized mirror delay, an output terminalcoupled to the clock tree and a control terminal for coupling the outputterminal to the first input terminal responsive to a control signalapplied to the control terminal having a first state and coupling theoutput terminal to the second input terminal responsive to the controlsignal having a second state; and a detector coupled to the controlinput of the switch and being operable to determine when thesynchronized mirror delay has stabilized, the detector being operable togenerate the control signal having the first state prior to determiningthe synchronized mirror delay has stabilized and to generate the controlsignal having the second state responsive to determining thesynchronized mirror delay has stabilized.
 22. The digital signal capturecircuit of claim 21 wherein the detector comprises a logic circuit thatis operable to generate the control signal having the first state priorto the lapse of a predetermined number of periods of the external clocksignal, and is operable to generate the control signal having the secondstate responsive to the lapse of the predetermined number of periods ofthe external clock signal.
 23. The digital signal capture circuit ofclaim 22 wherein the predetermined number of periods of the externalclock signal is two periods of the external clock signal.
 24. Thedigital signal capture circuit of claim 17 further comprising: a finedelay line coupled between the output of the synchronized mirror delayand the clock tree, the fine delay line varying the delay of the finedelay line responsive to a delay control signal applied to a controlterminal of the fine delay line; a phase detector having a first inputterminal to an output terminal of the fine delay line, a second inputterminal, and an output terminal coupled to the control terminal of thefine delay line, the phase detector generating the delay control signalas a function of the phase difference between signal applied to itsfirst and second input terminals; and a delay model circuit operable toprovide a predetermined delay, the delay model circuit coupling thedelayed feedback signal from the clock tree to the second input terminalof the phase detector.
 25. The digital signal capture circuit of claim24 wherein the delay model circuit comprises a delay circuit having adelay with a delay magnitude that is substantially less than the delayof the synchronized mirror delay.
 26. The digital signal capture circuitof claim 17 wherein the digital signal comprises a digital signalcorresponding to a data bit.
 27. A memory device, comprising: an arrayof memory cells arranged in rows and columns; a row address decodercoupled to receive a row address signal and to enable a correspondingrow of memory cells in the array; a column address decoder coupled toreceive a column address signal and to enable a corresponding column ofmemory cells in the array; a command decoder operable to receive memorycommands from a command bus and to generate control signalscorresponding to respective memory commands; a data path coupled betweenthe array of memory cells and a data bus terminal, the data pathincluding a latch operable to latch data into or out of the memorydevice responsive to a clock signal applied to a clock terminal of thelatch; a synchronized mirror delay having an output terminal, ameasurement delay line input terminal, and a variable delay line inputterminal; an input buffer having an input terminal coupled to receive anexternal clock signal and an output terminal coupled to the variabledelay line input terminal of the synchronized mirror delay; and a clocktree coupling the output terminal of the synchronized mirror delay tothe clock terminal of the latch, the clock tree having a feedback nodecoupled to the measurement delay line input terminal to provide adelayed feedback signal corresponding to a signal coupled from thefeedback node of the clock tree.
 28. The memory device of claim 27wherein the input buffer delays the external clock signal by a firstdelay value; and wherein the clock skew compensation circuit furthercomprises a model delay circuit coupled between the feedback node of theclock tree and the measurement delay line input terminal, the modeldelay circuit providing a delay substantially equal to the first delayvalue so that the delayed feedback signal applied to the measurementdelay line input terminal corresponds to the signal from the feedbacknode of the clock tree delayed by substantially the first delay value.29. The memory device of claim 28 further comprising a clock drivercoupling the output of the synchronized mirror delay to the clock tree,the clock driver providing a delay of a second delay value, and whereinthe model delay circuit further provides a delay substantially equal tothe second delay value so that the delayed feedback signal applied tothe measurement delay line input terminal corresponds to the signal fromthe feedback node of the clock tree delayed by substantially the sum ofthe first delay value and the second delay value.
 30. The memory deviceof claim 27 wherein the input buffer delays the external clock signal bya first delay value, and wherein the digital signal is coupled to thelatch through a driver circuit that delays the digital signal by asecond delay value, and wherein the clock skew compensation circuitfurther comprises a model delay circuit coupled between the feedbacknode of the clock tree and the measurement delay line input terminal,the model delay circuit providing a delay substantially equal to thefirst delay value less the second delay value.
 31. The memory device ofclaim 27 further comprising: a switch having a first input terminalcoupled to receive the external clock signal, a second input terminalcoupled to the output terminal of the synchronized mirror delay, anoutput terminal coupled to the clock tree and a control terminal forcoupling the output terminal to the first input terminal responsive to acontrol signal applied to the control terminal having a first state andcoupling the output terminal to the second input terminal responsive tothe control signal having a second state; and a detector coupled to thecontrol input of the switch and being operable to determine when thesynchronized mirror delay has stabilized, the detector being operable togenerate the control signal having the first state prior to determiningthe synchronized mirror delay has stabilized and to generate the controlsignal having the second state responsive to determining thesynchronized mirror delay has stabilized.
 32. The memory device of claim31 wherein the detector comprises a logic circuit that is operable togenerate the control signal having the first state prior to the lapse ofa predetermined number of periods of the external clock signal, and isoperable to generate the control signal having the second stateresponsive to the lapse of the predetermined number of periods of theexternal clock signal.
 33. The memory device of claim 32 wherein thepredetermined number of periods of the external clock signal is twoperiods of the external clock signal.
 34. The memory device of claim 27further comprising: a fine delay line coupled between the output of thesynchronized mirror delay and the clock tree, the fine delay linevarying the delay of the fine delay line responsive to a delay controlsignal applied to a control terminal of the fine delay line; a phasedetector having a first input terminal to an output terminal of the finedelay line, a second input terminal, and an output terminal coupled tothe control terminal of the fine delay line, the phase detectorgenerating the delay control signal as a function of the phasedifference between signal applied to its first and second inputterminals; and a delay model circuit operable to provide a predetermineddelay, the delay model circuit coupling the delayed feedback signal fromthe clock tree to the second input terminal of the phase detector. 35.The memory device of claim 34 wherein the delay model circuit comprisesa delay circuit having a delay with a delay magnitude that issubstantially less than the delay of the synchronized mirror delay. 36.The memory device of claim 27 wherein the memory device comprises adynamic random access memory.
 37. A computer system, comprising:computer circuitry operable to perform computing functions; at least oneinput device coupled to the computer circuitry; at least one outputdevice coupled to the computer circuitry; at least one data storagedevices coupled to the computer circuitry; and a dynamic random accessmemory, comprising: an array of memory cells arranged in rows andcolumns; a row address decoder coupled to receive a row address signaland to enable a corresponding row of memory cells in the array; a columnaddress decoder coupled to receive a column address signal and to enablea corresponding column of memory cells in the array; a command decoderoperable to receive memory commands from a command bus and to generatecontrol signals corresponding to respective memory commands; a data pathcoupled between the array of memory cells and a data bus terminal, thedata path including a latch operable to latch data into or out of thememory device responsive to a clock signal applied to a clock terminalof the latch; a synchronized mirror delay having an output terminal, ameasurement delay line input terminal, and a variable delay line inputterminal; an input buffer having an input terminal coupled to receive anexternal clock signal and an output terminal coupled to the variabledelay line input terminal of the synchronized mirror delay; and a clocktree coupling the output terminal of the synchronized mirror delay tothe clock terminal of the latch, the clock tree having a feedback nodecoupled to the measurement delay line input terminal to provide adelayed feedback signal corresponding to a signal coupled from thefeedback node of the clock tree.
 38. The computer system of claim 37wherein the input buffer delays the external clock signal by a firstdelay value; and wherein the clock skew compensation circuit furthercomprises a model delay circuit coupled between the feedback node of theclock tree and the measurement delay line input terminal, the modeldelay circuit providing a delay substantially equal to the first delayvalue so that the delayed feedback signal applied to the measurementdelay line input terminal corresponds to the signal from the feedbacknode of the clock tree delayed by substantially the first delay value.39. The computer system of claim 38 further comprising a clock drivercoupling the output of the synchronized mirror delay to the clock tree,the clock driver providing a delay of a second delay value, and whereinthe model delay circuit further provides a delay substantially equal tothe second delay value so that the delayed feedback signal applied tothe measurement delay line input terminal corresponds to the signal fromthe feedback node of the clock tree delayed by substantially the sum ofthe first delay value and the second delay value.
 40. The computersystem of claim 37 wherein the input buffer delays the external clocksignal by a first delay value, and wherein the digital signal is coupledto the latch through a driver circuit that delays the digital signal bya second delay value, and wherein the clock skew compensation circuitfurther comprises a model delay circuit coupled between the feedbacknode of the clock tree and the measurement delay line input terminal,the model delay circuit providing a delay substantially equal to thefirst delay value less the second delay value.
 41. The computer systemof claim 37 further comprising: a switch having a first input terminalcoupled to receive the external clock signal, a second input terminalcoupled to the output terminal of the synchronized mirror delay, anoutput terminal coupled to the clock tree and a control terminal forcoupling the output terminal to the first input terminal responsive to acontrol signal applied to the control terminal having a first state andcoupling the output terminal to the second input terminal responsive tothe control signal having a second state; and a detector coupled to thecontrol input of the switch and being operable to determine when thesynchronized mirror delay has stabilized, the detector being operable togenerate the control signal having the first state prior to determiningthe synchronized mirror delay has stabilized and to generate the controlsignal having the second state responsive to determining thesynchronized mirror delay has stabilized.
 42. The computer system ofclaim 41 wherein the detector comprises a logic circuit that is operableto generate the control signal having the first state prior to the lapseof a predetermined number of periods of the external clock signal, andis operable to generate the control signal having the second stateresponsive to the lapse of the predetermined number of periods of theexternal clock signal.
 43. The computer system of claim 42 wherein thepredetermined number of periods of the external clock signal is twoperiods of the external clock signal.
 44. The computer system of claim37 further comprising: a fine delay line coupled between the output ofthe synchronized mirror delay and the clock tree, the fine delay linevarying the delay of the fine delay line responsive to a delay controlsignal applied to a control terminal of the fine delay line; a phasedetector having a first input terminal to an output terminal of the finedelay line, a second input terminal, and an output terminal coupled tothe control terminal of the fine delay line, the phase detectorgenerating the delay control signal as a function of the phasedifference between signal applied to its first and second inputterminals; and a delay model circuit operable to provide a predetermineddelay, the delay model circuit coupling the delayed feedback signal fromthe clock tree to the second input terminal of the phase detector. 45.The computer system of claim 44 wherein the delay model circuitcomprises a delay circuit having a delay with a delay magnitude that issubstantially less than the delay of the synchronized mirror delay. 46.The computer system of claim 37 wherein the memory device comprises adynamic random access memory.
 48. A method of generating an internalclock signal from an external clock signal, comprising: receiving theexternal clock signal; receiving a feedback signal resulting fromcoupling the internal clock signal through a clock tree, the feedbacksignal providing an indication of the delay of the internal clock signalpropagating through the clock tree; and delaying the external clocksignal to generate the internal clock signal, the external clock signalbeing delayed by a delay value corresponding to a predetermined numberof clock cycles of the external clock signal less the delay of theinternal clock signal indicated by the feedback signal.
 49. The methodof claim 48 further comprising initially generating the internal clocksignal directly from the external clock signals for a predeterminednumber of periods of the external clock signal.
 50. The method of claim48 wherein the act of delaying the external clock signal to generate theinternal clock signal comprises delaying the external clock signal inrelatively coarse delay increments, and wherein the method furthercomprises delaying the external clock signal in relatively fine delayincrements within each relatively coarse delay increment.
 51. A methodof capturing a digital signal, comprising: delaying a clock signal by adelay time to generate a delayed clock signal; coupling the delayedclock signal through a clock tree to a predetermined circuit node, thedelayed clock signal being delayed as it propagates thought the clocktree; capturing the digital signal responsive to the delayed clocksignal reaching the predetermined node; receiving a feedback signalresulting from coupling the delayed clock signal through the clock tree,the feedback signal providing an indication of the delay of the delayedclock signal propagating through the clock tree; and adjusting the delaytime to correspond to a predetermined number of clock cycles of theexternal clock signal less the delay of the delayed clock signalindicated by the feedback signal.
 52. The method of claim 51 wherein themethod is performed in an integrated circuit, and wherein the digitalsignal comprises an external signal applied to the integrated circuit.53. The method of claim 51 wherein the method is performed in anintegrated circuit, and wherein the digital signal comprises an internalsignal applied to an output terminal of the integrated circuit.
 54. Themethod of claim 51 further comprising initially generating the delayedclock signal directly from the clock signal for a predetermined numberof periods of the clock signal.
 55. The method of claim 51 wherein theact of delaying the clock signal to generate the delayed clock signalcomprises delaying the clock signal in relatively coarse delayincrements, and wherein the method further comprises delaying the clocksignal in relatively fine delay increments within each relatively coarsedelay increment.
 56. The method of claim 51 wherein the method isperformed in an integrated circuit, and wherein the clock signalcomprises a external clock signal applied to the integrated circuit.